1. Field of the Invention
The present invention relates to an integrated circuit apparatus having an SRAM cell array formed of CMOSFET and, particularly, to an integrated circuit apparatus capable of reducing the effects of latch-up that occurs in an SRAM cell array.
2. Description of Related Art
An integrated circuit having a complementary metal oxide semiconductor field effect transistor (CMOSFET) is susceptible to latch-up that an abnormal current flows between a power supply and a ground of the integrated circuit, caused by a parasitic bipolar transistor with a thyristor structure in CMOSFET turning ON upon application of an overvoltage to an input/output terminal or the like.
The reduction in a power supply voltage with miniaturization of an integrated circuit and the implementation of shallow trench isolation (STI) for device isolation have contributed to the improvement in latch-up resistance. At the same time, since a PN isolation interval decreases due to the miniaturization of an integrated circuit, the ability of a parasitic bipolar transistor that causes latch-up increases and therefore the problem of latch-up still remains. Further, since a gate length of MOSFET also decreases like in the parasitic bipolar, snap-back behavior is also likely to occur at a low voltage.
The problem of latch-up is particularly serious in an SRAM cell array that is composed of CMOS memory cells with a low density of a well potential contact and a substrate potential contact. Occurrence of latch-up in the SRAM cell array leads to not only breakdown of the data stored in the memory cell but also hard errors if the latch-up is left unsolved.
Technologies to prevent latch-up from occurring involve the followings. Approaches in layout technology include increasing the density of a well potential contact and a substrate potential contact, enlarging a PN isolation interval, and so on.
Approaches in device process technology include increasing impurity concentration, reducing electric resistance of a well and a substrate through optimization of an impurity profile, and so on. Other approaches use a P on P+ epitaxial wafer or Silicon on Insulating Substrate (SIS).
Further, approaches in circuit technology include placing a mechanism for blocking power supply in the event of latch-up in order to prevent hard errors from occurring due to latch-up. This technique is described in Japanese Unexamined Patent Publication No. 61-67952, 07-234799, 08-255872, for example.
Japanese Unexamined Patent Publication No. 61-67952 discloses a CMOS semiconductor apparatus that has resistance control means to detect the occurrence of latch-up and limit the supply of a power supply current. Upon detecting the occurrence of latch-up, the apparatus increases the resistance value of a resistor in a power supply circuit to place limitation on power supply current, thereby preventing large current from flowing into the circuit.
Japanese Unexamined Patent Publication No. 07-234799 discloses a latch-up protector that has a voltage controller for controlling the voltage for driving a load upon occurrence of latch-up.
Japanese Unexamined Patent Publication No. 08-255872 discloses an integrated circuit apparatus that divides an integrated circuit into functional blocks and places a latch-up detector in each of the divided functional blocks.
Besides the above techniques, a technique for avoiding the occurrence of latch-up in SRAM is described in Japanese Unexamined Patent Publication No. 2003-208800. Specifically, this technique supplies different voltages to a memory cell region and a peripheral circuit region in burn-in test of a semiconductor memory device so as to prevent the memory cell from breakdown due to the occurrence of latch-up during the burn-in test.
Further, T. Calin et al., IEEE TRANSACTIONS ON NUCLEAR SCIENCE, December 1995, Vol. 42, No. 6, pp. 1592-1598 discloses a technique of placing a circuit for detecting a weak current that occurs due to bit inversion in a memory cell in the event of soft errors in an SRAM cell array in each 1-bit sequence of the cell array.
The present invention, however, has recognized that the above techniques have the following problems. If latch-up occurs in an SRAM cell array, the effects of latch-up spread to all of a plurality of memory cells that receive power supply from a pair of power line and ground line. Thus, even if hard errors are avoided by placing a detector between the power line and ground line to detect latch-up and blocking power supply, data of the entire memory cells affected by latch-up can be lost. For example, in a conventional SRAM cell array, a pair of power supply line and ground line is placed in every 8-bit sequence. If latch-up occurs in such a cell array, the data retained in the entire memory cells of the 8-bit sequence supplied with power through the pair of power supply line and ground line is lost.